Most network routers today use specialized hardware, such as custom network processors, to handle the critical path tasks of processing incoming data packets and forwarding the data packets toward their destinations. Such specialized hardware is advantageous from a performance perspective since it enables a network router to perform wire-speed routing at the high data rates supported by modern physical transport standards (e.g., 10G, 40G, or 100G Ethernet). However, with current network processor designs, this performance benefit comes at the expense of hardware design complexity and extensibility.
For example, consider a conventional, hardware-based network processor that is designed to forward both unicast and multicast data traffic. Due to differences in routing protocols, the processor must typically implement, at the hardware level, distinct forwarding pipelines for unicast and multicast flows respectively. Even within the multicast context, the processor may need to implement multiple forwarding pipelines to support different Protocol Independent Multicast (PIM) standards (e.g., PIM Sparse Mode (PIM-SM), PIM Dense Mode (PIM-DM), Bidirectional PIM (PIM-BIDIR), and PIM Source-Specific Multicast (PIM-SSM)). This significantly complicates the processor's hardware design and requires pre-classification logic to determine which forwarding pipeline to use for a given data packet. This design complexity can also constrain the overall operating speed of the processor.
In addition, since the forwarding pipelines described above are generally static in nature, the pipelines are limited to supporting the specific routing functionality implemented at design-time. This means that conventional network processor designs cannot be extended to support routing protocol changes or new routing protocol standards.